1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to a method of consistently forming low resistance contact structures in vias configured between interconnect lines arranged on different interconnect levels.
2. Description of the Relevant Art
An integrated circuit consists of electronic devices electrically coupled by conductive trace elements, often called interconnect lines (i.e., interconnects). Interconnects are patterned from conductive layers formed on or above the surface of a silicon substrate. One or more conductive layers may be patterned to form one or more levels of interconnects vertically spaced from each other by one or more interlevel dielectric layers. Dielectric-spaced interconnect levels allow formations of densely patterned devices on relatively small surface areas. Interconnects on different levels are commonly coupled electrically using contact structures formed in vias (i.e., openings or holes etched through interlevel dielectric layers separating the interconnects).
The operating speed of an integrated circuit is limited by transistor switching times and signal propagation delays associated with signal lines along one or more critical signal paths through the circuit. A signal line formed between input/output terminals of an integrated circuit comprises interconnects, arranged on one or more levels, connected by contact structures (i.e., contacts) disposed between the interconnect levels. Resistance of each signal line is equal to the sum of the resistance values of the interconnect lines and the contacts making up the signal line. As feature sizes shrink, transistor switching times typically decrease while signal propagation delays of signal lines typically increase. In fact, the maximum operating speeds of integrated circuits with submicron feature sizes are typically limited by signal propagation delays associated with signal lines. Thus if the maximum operating speeds of integrated circuits are to increase as device dimensions shrink, the resistance values associated with interconnect lines and contacts must also be reduced to achieve the desired speed.
Following the formation and patterning of an interconnect level, an interlevel dielectric layer is deposited over the interconnect level. Prior to the formation and patterning of a subsequent interconnect level, vias are etched through the interlevel dielectric layer in locations where interconnects on different interconnect levels are to be electrically connected. Conductive material used to form a layer of interconnects is typically deposited on or above the surface of a silicon substrate by sputter deposition. As long as sputter deposition can adequately fill the vias, special via-filling procedures are not required.
In order to increase layout (i.e., packing) densities, advanced submicron fabrication technologies typically require a via-filling operation be incorporated into the process sequence prior to the deposition and patterning of subsequent interconnect levels. Following patterning of an interlevel dielectric layer to form vias, a layer of metal is typically formed over the interlevel dielectric layer until the vias are substantially filled with the metal. Portions of the metal layer over the interlevel dielectric layer are then removed. The remaining portions of the metal layer bounded exclusively within the vias form electrical contact structures between interconnects on different levels.
The metal tungsten (W) is commonly used to form metal "plugs" within the vias. Tungsten, however, does not adhere well to most common dielectric materials (e.g., silicon dioxide) used to form interlevel dielectric layers. As a result, a layer of titanium nitride (TiN) is typically deposited over an interlevel dielectric layer following patterning of the interlevel dielectric layer to form vias and prior to deposition of a W layer. The TiN layer becomes a "nucleating surface" for the subsequently deposited W layer, and the W layer adheres well to the TiN-coated interlevel dielectric layer. The W layer is deposited over the TiN layer to a thickness so as to substantially fill the vias. Portions of the W and TiN layers over substantially horizontal surfaces of the interlevel dielectric layer are then removed. The remaining portions of the W and TiN layers are bounded within the vias.
During TiN deposition, loose particles of TiN are sometimes formed which end up upon the exposed upper surfaces of semiconductor substrates. A portion of these TiN particles come to rest over via openings, preventing various chemically reactive species from entering the vias for the remainder of the TiN deposition period. As a result, TiN adhesion layers of adequate thickness are often not formed upon sidewalls and bottom surfaces of vias with openings blocked by TiN particles. Even if the TiN particles are removed from over the openings of vias after TiN deposition and before W deposition, W reactant species introduced during the subsequent W depositions will not adhere to the sidewalls and bottom surfaces of the vias due to the lack of adequate TiN adhesion layers. As a result, adequate W material is not deposited within affected vias, and the contact structures formed within affected vias display high electrical resistances. The integrated circuits containing such high resistance contact structures typically fail to meet performance requirements and must be rejected, lowering the yield of the wafer fabrication process.
It would thus be advantageous to have a method for consistently forming low resistance contact structures which ensures adequate TiN adhesion layer thickness despite the occurrences of TiN particles which block via openings during TiN depositions. The desired method would consistently produce low resistance contact structures by ensuring adequate plug material deposition within the vias. The number of integrated circuits which fail to meet performance requirements would be reduced, thereby increasing wafer fabrication process yields.